The pseudo SRAM has conventionally been known as a semiconductor memory device which includes DRAM as a basic element and which is configured to be operated quite similarly to SRAM. Such the pseudo SRAM is a memory of non-synchronous type in an external viewpoint. The pseudo SRAM includes DRAM as the basic element, for which reason it is necessary to periodically refresh memory data.
A conventional example of the non-synchronous semiconductor memory device including DRAM as the basic element will be described below with attracting a refresh circuit therein.
FIG. 16 shows a semiconductor memory device (the first prior art) of this non-synchronous type including DRAM as the basic element, which is also dislocated by the inventors in International Publication No. W001/41149A1. In this drawing, an address ADD is a signal given from the outside. The address ADD includes row addresses designating rows of a memory cell array to be described later, and column addresses designating columns thereof.
An address input system 1 latches the address ADD and outputs an internal address LADD. An address transition detector circuit (ATD) 2 detects any transition of the internal address LADD and outputs a one-shot pulse signal SATD. An address multiplexer (MUX) 3 outputs any one of the internal address LADD and a refresh address RADD to be described below as an address MADD.
A row decoder 60 decodes the address MADD for selecting a row of a memory cell array 70. The memory cell array 70 comprises a matrix array of memory cells similarly to those of the general-purpose DRAM. A sense amplifier 71 amplifies a data signal on a bit line for read operation. A column decoder 72 selects a column of the memory cell array 70. A pre-charge circuit (not illustrated) for bit lines is arranged which is accompanied to the sense amplifier 71.
A refresh timer circuit 8G times a period of time for refresh operations. A refresh control circuit 8H controls a series of refresh operations. Upon an external access, the refresh control circuit 811 generates a refresh control signal REFA for controlling the timings of the refresh operations and another refresh control signal REFB for controlling the timings of the self-refresh operations.
A refresh address generator circuit 8J generates am address RADD (hereinafter referred to as “refresh address”) to be used for the refresh operation. An internal pulse generator circuit 10 generates a row enable signal RE, a sense amplifier enable signal SE, a pre-charge enable signal PE, and a column enable signal CE.
In addition to the above-described circuits, there are further provided a circuit system for controlling read and write operations, another circuit system for generating a substrate potential of the memory cell array, and still another circuit system for reading and writing data from and into the memory cell array.
The refresh operations of the semiconductor memory device in accordance with the prior art shown in FIG. 16 will subsequently be described with reference to a timing chart of FIG. 17, wherein FIG. 17(a) shows timing waveforms of the refresh operation in the read mode, while FIG. 17(b) shows timing waveforms of the other refresh operation in the stand-by mode.
A. Refresh Operation in Read Mode:
In the read mode, this semiconductor memory device sequentially performs a refresh operation and a read operation in the same cycle in view of the specification thereof.
Namely, the address input system 1 latches the externally-given address A0 as the address ADD, and outputs this address A0 as the internal address LADD. The address transition detector circuit 2 detects the transition of the internal address LADD and then outputs the one-shot pulse signal SATD.
The refresh control circuit 8H receives the one-shot pulse signal SATD to start the refresh operation. After the refresh operation has been started, then the refresh address generator circuit 8J generates and outputs a refresh row address R0 as the refresh address RADD. An address multiplexer 3 supplies the refresh address RADD (namely the refresh row address R0) as the address MADD to the row decoder 60.
On the other hand, the internal pulse generator circuit 10 receives an input of a refresh control signal REFB from the refresh control circuit 8H, and outputs the row enable signal RE and the sense amplifier enable signal SE. The row decoder 60 receives inputs of the address MADD and the row enable signal RE and selects a word line designated by the refresh address R0 for a predetermined period of time defined by the row enable signal RE, whereby a data signal from a memory cell connected to the selected word line appears on a bit line in a memory cell array 70, and the sense amplifier 71 amplifies this data signal and re-writes the amplified signal into the memory cell. As a result, data for memory cells on a single row designated by the refresh row address R0 has been refreshed. Subsequently, in each cycle, the refresh will be made to each row designated by each refresh address sequentially generated by the refresh address generator circuit 8J.
After the refresh operation has been finished to the row designated by the refresh row address R0, then the read operation is made in the same cycle. Namely, the word line designated by the internal address LADD is selected, whereby data are read from the memory cells connected to this word line. Concretely, the address multiplexer 3 receives the internal address LADD outputted from the address input system 1, and then supplies the internal address LADD as the address MADD to the row decoder 60. The row decoder 60 selects a word line designated by an input row address X0 as the address MADD. Thereafter, the sense amplifier 71 amplifiers the data signal having appeared on the bit line in the memory cell array 70, whereby the data stored in the memory cell are read out.
As described above, in the read mode, the transition of the externally supplied address is detected by the address transition detector circuit (ATD) 2, thereby to start the refresh and read operations. If a last request of access from the outside appears and a counted past time becomes beyond a predetermined refresh time period, after the last detection of the address transition is made by the address transition detector circuit (ATD) 2, then the self-refresh operation starts even no external access request is present.
B. Refresh Operation in Stand-By Mode:
In the stand-by mode, the detection of the address transition by the address transition detector circuit (ATD) 2 is stopped, so that even if the address transition appears, then only the self-refresh operation is made without any read operation. Concretely, in the stand-by mode, the refresh timer circuit 8G times a time interval of the self-refresh operations. The refresh control circuit 8H enables the refresh address generator circuit 8J to generate the refresh row address R0 as the refresh address RADD at a timing obtained through timing operation by the refresh timer circuit 8G. The address multiplexer 3 receives a refresh row address R0 as the refresh address RADD and supplies the refresh row address R0 as the address MADD to the row decoder 60.
On the other hand, the refresh control circuit 8H outputs the refresh control signal REFB for enabling the internal pulse generator circuit 10 to generate the row enable signal RE at an appropriate timing. The row decoder 60 receives the refresh row address R0 as the address MADD from the address multiplexer 3, and then selects a word line designated by the refresh row address R0 for a predetermined period of time defined by the row enable signal RE. Thereafter, data from the memory cells connected to the selected word line are amplified by the sense amplifier and then rewritten into the memory cells. Subsequently, in the stand-by mode, according to the timings generated by the refresh timer circuit 8G, sequential refresh operations are made to rows one-by-one designated by the respective refresh addresses sequentially generated by the refresh address generator circuit 8J.
The above-described conventional semiconductor memory device (the first prior art) is provided with a circuit for adjusting an external access and a self-refresh so that the self-refresh is made in the access mode, whereby the semiconductor memory device may be operable similarly to the non-synchronous SRAM without external control to the refresh. Notwithstanding, in the access for read and write operations, an external refresh is made by supplying a refresh timing from the outside, while in the stand-by mode, a self-refresh is made. A variety of conventional proposals has been made to such the semiconductor memory device.
In Japanese laid-open patent publication No. 1-159893 (the second prior art), it is mentioned that a refresh cycle for self-refresh is longer than another refresh cycle for external refresh in order to reduce a power consumption for the self-refresh.
In Japanese laid-open patent publication No. 4-259986 (the third prior art), it is mentioned that since the hold ability of the memory cell is dropped upon drop of the power voltage, a cycle setting circuit is provided for setting automatically a self-refresh cycle, depending upon variation of the power voltage, so that the self-refresh cycle is set shorter under the low power voltage, while the self-refresh cycle is set longer under the high power voltage.
By the way, the stand-by mode strictly limits the current consumption depending upon its specification, and particularly, a small current comsumption is desired for application to mobile terminals. Notwithstanding, in accordance with the above-described prior arts, in the stand-by mode, a single word line is selected for one-time refresh operation (refresh operation for a single row) similarly to the refresh operations in the active mode. For this reason, all the circuit systems associated with the refresh operations are operated for every refresh for one-row. This makes it difficult to effectively reduce the current consumption associated with the refresh operation.
An extension of the refresh cycle reduces the frequency of operations of the circuit systems associated with the refresh operations in order to reduce the current consumption. In accordance with the above-described first prior art, it is necessary that the refresh operations are made for all rows by sequentially selecting all word lines within a predetermined period of time which ensures the hold of data in the memory cells. This means that the time for each refresh operation is limited. This makes it difficult to effectively extend the refresh cycle and effectively reduce the current consumption.
In the above-circumstances, it is an object of the present invention to provide a semiconductor memory device which is capable of effectively reducing the current comsumption associated with the self-refresh operation in the stand-by mode.